Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B840F1024IQ100 /QSPI0 /CONFIG

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CONFIG

31282724232019161512118743000000000000000000000000000000000000000000 (ENBSPI)ENBSPI0 (SELCLKPOL)SELCLKPOL0 (SELCLKPHASE)SELCLKPHASE0 (PHYMODEENABLE)PHYMODEENABLE0 (ENBDIRACCCTLR)ENBDIRACCCTLR0 (ENBLEGACYIPMODE)ENBLEGACYIPMODE0 (PERIPHSELDEC)PERIPHSELDEC0PERIPHCSLINES0 (WRPROTFLASH)WRPROTFLASH0 (ENBAHBADDRREMAP)ENBAHBADDRREMAP0 (ENTERXIPMODE)ENTERXIPMODE0 (ENTERXIPMODEIMM)ENTERXIPMODEIMM0MSTRBAUDDIV0 (ENABLEAHBDECODER)ENABLEAHBDECODER0 (ENABLEDTRPROTOCOL)ENABLEDTRPROTOCOL0 (PIPELINEPHY)PIPELINEPHY0 (CRCENABLE)CRCENABLE0 (DUALBYTEOPCODEEN)DUALBYTEOPCODEEN0 (IDLE)IDLE

Description

Octal-SPI Configuration Register

Fields

ENBSPI

QSPI Enable

SELCLKPOL

Clock Polarity, CPOL

SELCLKPHASE

Clock Phase, CPHA

PHYMODEENABLE

PHY Mode Enable

ENBDIRACCCTLR

Enable Direct Access Controller

ENBLEGACYIPMODE

Legacy IP Mode Enable

PERIPHSELDEC

Peripheral Select Decode

PERIPHCSLINES

Peripheral Chip Select Lines

WRPROTFLASH

Write Protect Flash Pin

ENBAHBADDRREMAP

Enable Address Remapping

ENTERXIPMODE

Enter XIP Mode on Next READ

ENTERXIPMODEIMM

Enter XIP Mode Immediately

MSTRBAUDDIV

Master Mode Baud Rate Divisor

ENABLEAHBDECODER

Enable Address Decoder

ENABLEDTRPROTOCOL

Enable DTR Protocol

PIPELINEPHY

Pipeline PHY Mode Enable

CRCENABLE

CRC Enable Bit

DUALBYTEOPCODEEN

Dual-byte Opcode Mode Enable Bit

IDLE

Serial Interface and Low Level SPI Pipeline is IDLE

Links

() ()